Demonstration of p-type In0.7Ga0.3As/GaAs0.35Sb0.65 and n-type GaAs0.4Sb0.6/In0.65Ga0.35As Complimentary Heterojunction Vertical Tunnel FETs for Ultra-Low Power Logic

نویسندگان

  • R. Pandey
  • H. Madan
  • H. Liu
  • V. Chobpattana
  • M. Barth
  • B. Rajamohanan
  • M. J. Hollander
  • T. Clark
  • K. Wang
  • J- H. Kim
  • D. Gundlach
  • K. P. Cheung
  • J. Suehle
  • R. Engel-Herbert
  • S. Stemmer
  • S. Datta
چکیده

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تاریخ انتشار 2015